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s3c8639/c863a/p863a product overview 1- 1 1 product overview sam8 product family samsung's sam8 family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu with a wide range of integrated peripherals, in variou s mask-programmable rom sizes. analog its major cpu features are : ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode release by interrupt ? built-in basic timer with watchdog function the sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum of four cpu clocks) can be assigned to specific interrupt levels. s3c8639/c863a/p863a microcontrollers s3c8639/c863a/p863a single-chip 8-bit microcontroller s are based on the powerful sam8 cpu architecture. the internal register file is logically expanded to incre ase the on-chip register space. s3c8639/c863a/p863a contain 32/48 k bytes of on- chip program rom. in line with samsung's modular design approach, the following peripherals are integrated with the sam8 core: ? f our programmable i/o ports (total 27 pins) ? one 8-bit basic timer for oscillation stabilization and watchdog functions ? one 8-bit general-purpose timer/counter with selectable clock sources ? one interval timer ? one 12 -bit counter with selectable clock sources, including hsync or csync input ? pwm block with seven 8-bit pwm circuits ? sync processor block (for vsync and hsync i/o, csync input, and clamp signal output) ? ddc multi-master and slave-only iic-bus ? 4-channel a/d convert er (8-bit resolution) s3c8639/c863a/p863a are a versatile microcontroller s which are ideal for use in multi-sync monitors or in general-purpose applications that require sophisticated timer/counter, pwm, sync signal processing, a/d converter, and multi-master iic-bus support with ddc. they are available in a 42-pi n sdip or a 44 -pin qfp package. otp s3c8639/c863a microcontrollers are also available in otp (one time programmable) version named, s3p863a. s3p863a microcontroller has an on-chip 48-kbyte one-time-programmable eprom instead of masked rom. s3p863a is comparable to s3c8639/c863a, both in function and pin configuration except its rom size.
product overview s3c8639/c863a/p863a 1- 2 features cpu ? sam 88rc cpu core memory ? s3c8639: 32-kbyte internal program memory (rom) S3C863A: 48-kbyte internal program memory (rom) ? s3c8639: 784-byte general-purpose register area S3C863A: 1040- byte general-purpose register area instruction set ? 78 instructions ? idle and stop instructions added for power-down modes instruction execution time ? minimum 333 ns (with 12 mhz cpu clock) interrupts ? ten interrupt sources/vectors ? eight interrupt level ? fast interrupt feature general i/o ? four i/o ports (total 27pins) 8-bit basic timer ? programmable timer for oscillation stabilization interval control or watchdog timer function ? three selective internal clock frequencies timer/counters ? one 8-bit t imer/counter with several clock sources (capture mode) ? one 12-bit counter with h-/c-sync and several clock sources ? one interval timer low voltage reset (lvr) ? lvr level is 2.4 v 200 mv pulse width modulator (pwm) ? 8-bit pwm: 7-ch (6-bit basic frame with 2-bit extension) sync-processor block ? vsync-i, hsync-i, csync-i input and vsync-o, hsync-o, clamp-o output pins ? programmable pseudo sync signal generation ? auto sog detection ? auto h-/v-sync polarity detection ? composite sync detection ddc multi-master iic-bus 1-ch ? serial peripheral interface ? support for display data channel (ddc1/ddc2b/ddc2bi/ddc2b+) slave only iic-bus 1-ch ? serial peripheral interface a/d converter ? 4-channel; 8-bit resolution oscillator frequency ? 8 mhz to 12 mhz crystal operation ? internal max. 12 mhz cpu clock operating temperature range ? ? 40 c to + 85 c operating voltage range ? 3.0 v to 5.5 v package types ? 42-pin sdip, 44-pin qfp
s3c8639/c863a/p863a product overview 1- 3 block diagram port 0 p0.0-p0.7/int0-int2 i/o port and interrupt control 32/48- kbyte rom 784/1040- byte register file sam8 cpu port 2 port 1 p1.0-p1.2 p2.0-p2.7 v dd1 , v dd2 v ss1 , v ss2 test reset int0-int2 adc port 3 p3.0-p3.7 slave only iic-bus ad0-ad3 scl1 sda1 main osc 8-bit pwm (7-ch) sync- processor x out x in pwm0 pwm6 8-bit counter (timer m0) tm0cap vsync-i hsync-i csync-i vsync-o hsync-o clamp-o 12-bit counter (timer m1) interval timer (timer m2) multi-master iic-bus and ddc1/2b/2bi/2b+ scl0 sda0 * s3c8639 - 32 kbyte rom - 784 byte ram * S3C863A - 48 kbyte rom - 1040 byte ram figure 1- 1. block diagram
product overview s3c8639/c863a/p863a 1- 4 pin assignments p0.0/int0 p0.1/int1 p0.2/int2 p0.3 p0.4/tm0cap p0.5 p0.6 p0.7 p1.0/sda1 p1.1/scl1 v dd1 v ss1 x out x in test (gnd) sda0 scl0 reset p1.2 p2.0/pwm0 p2.1/pwm1 s3c8639 /c863a (42-sdip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0/ad0 v dd2 v ss2 p2.7/csync-i (sog) hsync-i vsync-i vsync-o hsync-o clamp-o p2.6/pwm6 p2.5/pwm5 p2.4/pwm4 p2.3/pwm3 p2.2/pwm2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 note: the test pin must connect to v ss (gnd) in the normal operation mode. figure 1- 2 . s3c8639/c863a 42-sdip pin assignment
s3c8639/c863a/p863a product overview 1- 5 scl0 reset p1.2 p2.0/pwm0 p2.1/pwm1 p2.2/pwm2 n.c. p2.3/pwm3 p2.4/pwm4 p2.5/pwm5 p2.6/pwm6 p3.2/ad2 p3.1/ad1 p3.0/ad0 v dd2 v ss2 p2.7/csync-i (sog) hsync-i vsync-i vsync-o hsync-o clamp-o p0.4/tm0cap p0.3 p0.2/int2 p0.1/int1 n.c. p0.0/int0 p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p0.5 p0.6 p0.7 p1.0/sda1 p1.1/scl1 v dd1 v ss1 x out x in test (gnd) sda0 s3c8639 /c863a 44-qfp (top view) 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 note: the test pin must connect to v ss (gnd) in the normal operation mode. figure 1- 3 . s3c8639/c863a 44-qfp pin assignment
product overview s3c8639/c863a/p863a 1- 6 pin descriptions table 1-1. s3c8639/c863a pin descriptions pin names pin type pin description circuit type sdip pin numbers shared functions p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 i/o general-purpose, 8-bit i/o port. shared functions include three external interrupt inputs and i/o for timer m0. selective configuration of port 0 pins to input or output mode is supported. d-1 d-1 d-1 d-1 d-1 d-1 d-1 d-1 1 2 3 4 5 6 7 8 int0 int1 int2 tm0cap p1.0 p1.1 p1.2 i/o general-purpose, 8-bit i/o port. selective configuration is available for port 1 pins to input, push-pull output, n-channel open-drain mode, or iic-bus clock and data i/o. e-1 e-1 e-1 9 10 19 sda1 scl1 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 i/o general-purpose, 8-bit i/o port selective configuration of port 2 pins to input or output mode is supported. the port 2 pin circuits are designed to push-pull pwm output and csync (sog) signal input. d-1 d-1 d-1 d-1 e-1 e-1 e-1 d-1 20 21 22 23 24 25 26 32 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 csync-i p3.0?p3.3 p3.4?p3.7 i/o general-purpose, 8-bit i/o port selective configuration port 3 pins to input or output mode is supported. multiplexed for alternative use as a/d converter inputs ad0?ad3. e-1 e 35?38 39?42 ad0? ad3 hsync-i vsync-i clamp-o hsync-o vsync-o sda0 scl0 i i o o o i/o i/o the pins are sync processor signal i/o and iic- bus clock and data i/o. a-3 a-3 a a a g-3 g-3 31 30 27 28 29 16 17 ? v dd1 , v ss1 , v dd2 , v ss2 ? power pins ? ? 11, 12 34, 33 ? x in , x out ? system clock i/o pins ? 14, 13 ? reset i system reset pin b 18 ? test i factory test pin input 0 v: normal operation , 5 v: factory test mode ? 15 ?
s3c8639/c863a/p863a product overview 1- 7 pin circuits diagram data v ss output v dd figure 1- 4 . pin circuit type a reset v dd 280 k w noise filter figure 1- 6 . pin circuit type b ( reset ) input v ss output v ss 300 k w typical v dd figure 1- 5 . pin circuit type a-3 data or other function v ss output output disable digital input, ttl input note: the noise filter must be built in the external interrupts. v dd figure 1-7. pin circuit type d-1
product overview s3c8639/c863a/p863a 1- 8 data v ss output typical 47 k w pull-up enable v dd v dd output disable open drain input figure 1-8. pin circuit type e v ss output data input figure 1-10. pin circuit type g-3 data v ss output v dd output disable open drain digital input or adc input figure 1-9. pin circuit type e-1
s3c8639/c863a/p863a electrical data 19- 1 19 electrical data overview in this section, s3c8639/c863a electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. e lectrical characteristics ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? i/o capacitance ? a/d converter electrical characteristics ? a.c. electrical characteristics ? input timing measurement points for p0.0?p0.2 and tm0cap ? oscillation characteristics ? oscillation stabilization time ? clock timing measurement points for x in ? schmitt trigger characteristics ? power-on reset circuit characteristics
electrical data s3c 8639/c863a/p863a 19- 2 table 19-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i1 type g-3 (n-channel open drain) ? 0.3 to + 7.0 v i2 all port pins except v i1 ? 0.3 to v dd + 0.3 output voltage v o all output pins ? 0.3 to v dd + 0.3 output current high i oh one i/o pin active ? 10 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 total pin current except port 3 + 100 sync-processor i/o pins and iic-bus clock and data pins + 150 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 table 19-2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit input high v ih1 all input pins except v ih2 , v ih3 and v ih4 0.8 v dd ? v dd v voltage v ih2 x in v dd ?0.5 v dd v ih3 ttl input ( hsync-i, vsync-i, and csync-i) 2.0 v dd v ih4 scl0/sda0, scl1/sda1 0.7v dd v dd input low v il1 all input pins except v il2 and v il3 ? 0.2 v dd voltage v il2 x in 0.4 v il3 ttl input ( hsync-i, vsync-i, and csync-i) 0.8 v il4 scl0/sda0, scl1/sda1 0.3v dd output high voltage v oh1 v dd = 5 v 10%; i oh = ? 15 ma; port 3.6?3.7 v dd ? 1.0 ? v oh2 v dd = 5 v 10%; i oh = ? 4 ma; port 1.2, port 3.0?3.5 v oh3 v dd = 5 v 10%; i oh = ? 2 ma; port 0, 2, clamp-o, h, and vsync-o v oh4 v dd = 5 v 10%; i oh = ? 6 ma; port 1.0?p1.1, scl0 and sda0
s3c8639/c863a/p863a electrical data 19- 3 table 19-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit output low voltage v ol1 v dd = 5 v 10%; i ol = 15 ma port 3.6 ?3.7 ? ? 0.4 v v ol2 v dd = 5 v 10%; i ol = 4 ma port 3.0?3.5 and port 1.2 0.4 v ol3 v dd = 5 v 10%; i ol = 2 ma port 0, 2, clamp-o, h, and vsync-o 0.4 v ol4 v dd = 5 v 10%; i ol = 6 ma port 1.0?1.1; scl0 and sda0 0.6 input high leakage current i lih1 v in = v dd all input pins except x in , x out ? ? 3 a i lih2 v in = v dd ; x out only ? ? 20 i lih3 v in = v dd ; x in only 2.5 6 20 input low leakage current i lil1 v in = 0 v; all input pins except x in , x out , reset , hsynci & vsynci ? ? ? 3 i lil2 v in = 0 v; x out only ? ? ? 20 i lil3 v in = 0 v; x in only ? 2.5 ? 6 ? 20 output high leakage current i loh1 v out = v dd ? ? 3 output low leakage current i lol1 v out = 0 v ? ? ? 3 pull-up resistor r u1 v in = 0 v; v dd = 5 v 10% ports 3.7?3.4 20 47 80 k w r u2 v in = 0 v; v dd = 5 v 10% reset only 150 280 480 pull-down resistor r d v in = 0 v; v dd = 5 v 10% hsynci & vsynci 150 300 500 supply current (note) i dd1 v dd = 5 v 10% operation mode; 12 mhz crystal c1 = c2 = 22pf ? 10 20 ma i dd2 v dd = 5 v 10% idle mode; 12 mhz crystal c1 = c2 = 22pf 4 8 i dd3 v dd = 5 v 10% stop mode 100 150 a note: supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.
electrical data s3c 8639/c863a/p863a 19- 4 table 19-3. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2 ? 5.5 v data retention supply current i dddr stop mode, v dddr = 2.0 v ? ? 5 a notes : 1. during the oscillator stabilization wait time (t wait ), all cpu operations must be stopped. 2. supply current does not include drawn through internal pull?up resistors and external output current loads. note: t wait is the same as 4096 x 16 x 1/f osc . execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilzation time data retention mode t wait reset v dd normal operating mode figure 19-1. stop mode release timing when initiated by a reset table 19-4. input/output capacitance (t a = ?40 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io
s3c8639/c863a/p863a electrical data 19- 5 table 19-5. a/d converter electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 8 ? bit total accuracy v dd = 5 v conversion time = 5 m s ? ? 2 lsb integral linearity error ile av ref = 5 v ? 1 differential linearity error dle av ss = 0 v ? 1 offset error of top eot 1 2 offset error of bottom eob 0.5 2 conversion time (1) t con 8 bit conversion 40 x n/f osc (3) , n=1,4,8,16 20 ? 170 m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 1000 ? m w analog reference voltage av ref ? 2.5 ? v dd v analog ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av ref = v dd = 5v ? ? 10 m a analog block current (2) i adc av ref = v dd = 5v ? 1 3 ma av ref = v dd = 3v 0.5 1.5 ma av ref = v dd = 5v when power down mode 100 500 na notes: 1. "conversion time" is the time required from the moment a conversion operation starts until it ends. 2. i adc is an operating current during the a/d conversion. 3. f osc is the main oscillator clock.
electrical data s3c 8639/c863a/p863a 19- 6 table 19-6. a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5v) parameter symbol conditions min typ max unit noise filter t nf1h t nf1l int0?2 and tm0cap (rc delay) 300 ? ? ns t nf2 reset only (rc delay) 1000 ? ? t nf1h t nf1l 0.8 v dd 0.2 v dd t nf2 figure 19-2. input timing measurement points for p0.0?p0.2 and tm0cap
s3c8639/c863a/p863a electrical data 19- 7 table 19-7. oscillation characteristics (t a = ? 40 c + 85 c) oscillator clock circuit conditions min typ max unit main crystal or ceramic c2 c1 x in x out v dd = 3.0 v to 5.5 v 8 ? 12 mhz external clock (main) x in x out v dd = 3.0 v to 5.5 v 8 ? 12 mhz note : the maximum oscillator frequency is 12 mhz. if you use an oscillator frequency higher than 12 mhz, you cannot select a non-divided cpu clock using clkcon settings. that is, you must select one of the divide-by values. table 19-8. oscillation stabilization time (t a = ? 40 c + 85 c, v dd = 3.0 v to 5.5 v) oscillator test condition min typ max unit crystal v dd = 3.0 v to 5.5 v ? ? 20 ms ceramic v dd = 3.0 v to 5.5v ? ? 10 external clock x in input high and low level width (t xh , t xl ) 25 ? 500 ns note : oscillation stabilization time is the time required for the cpu clock to return to its normal oscillation frequency after a power-on occurs, or when stop mode is released. x in t xh t xl 1/fx v dd - 0.5 v 0.4 v figure 19-3. clock timing measurement points for x in
electrical data s3c 8639/c863a/p863a 19- 8 a = 0.2 v dd b = 0.4 v dd c = 0.6 v dd d = 0.8 v dd v dd v out v ss v in a b c d figure 19-4. schmitt trigger characteristics (normal port; except ttl input) table 19-9. power-on reset circuit characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit power-on reset release voltage v odlvd 2.7 ? 5.5 v power-on reset detection voltage v lvd 2.2 2.4 2.6 v power supply voltage rise time t r 10 ? (1) us power supply voltage off time t off 10 ? ? ms power-on reset circuit consumption current (2) i ddpr v dd = 5 v 10% 100 150 m a v dd = 3 v 60 100 m a notes: 1. 2 16 /f osc (= 5.46 ms at f osc /12mhz) 2. current contained when power-on reset circuit is provided internally.
s3c8639/c863a/p863a electrical data 19- 9 t off t r v ddlvd v lvd v dd figure 19-5. power-on reset timing
s3c8639/c863a/p863a mechanical data 20- 1 20 mechanical data overview the s3c8639/c863a microcontroller is available in a 42-pin sdip package ( samsung part number 42-sdip- 600) and a 44 -qfp package ( samsung part number 44-qfp-1010b). note : dimensions are in millimeters. 39.50 max 39.10 0 .2 0.50 0.1 1.778 (1.77) 0.51 min 3.30 0.3 3.50 0.2 5.08 max 42-sdip-600 0-15 1.00 0.1 0.25 + 0.1 - 0.05 15.24 14.00 0 .2 #42 #22 #21 #1 figure 20- 1. 42-pin sdip package mechanical data (42-sdip-600)
mechanical data s3c8639/c863a/p863a 20- 2 44-qfp-1010b #44 note : dimensions are in millimeters. 10.00 0.2 13.20 0.3 10.00 0.2 13.20 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 max 0.80 0.20 0.05 min 2.05 0.10 2.30 max 0.15 + 0.10 - 0.05 0-8 figure 20- 2. 44-pin qfp package mechanical data (44-qfp-1010b)
s3c8639/c863a/p863a s3p863a otp 21- 1 21 s3p863a otp overview the s3p863a single-chip cmos microcontroller is the otp (one time programmable) version of the s3c8639/c863a microcontrollers. it has an on-chip eprom instead of masked rom. the eprom is accessed by serial data format. the s3p863a is fully compatible with the s3c8639/c863a, both in function and in pin configuration. because of its simple programming requirements, the s3p863a is ideal for use as an evaluation chip for the s3c8639/c863a. p0.0/int0 p0.1/int1 p0.2/int2 p0.3 p0.4/tm0cap p0.5 p0.6 p0.7 sdat /p1.0/sda1 sclk /p1.1/scl1 v dd1 v ss x out x in v pp /test (gnd) sda0 scl0 reset /reset p1.2 p2.0/pwm0 p2.1/pwm1 s3p863a 42-sdip (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0/ad0 v dd2 v ss2 p2.7/csync-i (sog) hsync-i vsync-i vsync-o hsync-o clamp-o p2.6/pwm6 p2.5/pwm5 p2.4/pwm4 p2.3/pwm3 p2.2/pwm2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 note: the bolds indicate an otp pin name. figure 21-1. s3p863a pin assignments (42-sdip package)
s3p863a otp s3c8639/c863a/p863a 21- 2 p0.5 p0.6 p0.7 sdat /p1.0/sda1 sclk /p1.1/scl1 v dd1 v ss1 x out x in v pp /test (gnd) sda0 s3p863a 44-qfp (top view) 1 2 3 4 5 6 7 8 9 10 11 p0.4/tm0cap p0.3 p0.2/int2 p0.1/int1 n.c. p0.0/int0 p3.7 p3.6 p3.5 p3.4 p3.3/ad3 44 43 42 41 40 39 38 37 36 35 34 p3.2/ad2 p3.1/ad1 p3.0/ad0 v dd2 v ss2 p2.7/csync-i (sog) hsync-i vsync-i vsync-o hsync-o clamp-o 33 32 31 30 29 28 27 26 25 24 23 scl0 reset / reset p1.2 p2.0/pwm0 p2.1/pwm1 p2.2/pwm2 n.c. p2.3/pwm3 p2.4/pwm4 p2.5/pwm5 p2.6/pwm6 12 13 14 15 16 17 18 19 20 21 22 note: the bolds indicate an otp pin name. figure 21-2. s3p863a pin assignments (44-qfp package)
s3c8639/c863a/p863a s3p863a otp 21- 3 table 21-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p1.0 sdat 9 (4) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p1.1 sclk 10 (5) i serial clock pin. input only pin. test v pp (test) 15 (10) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 18 (13) i chip initialization v dd1 /v ss1 v dd1 /v ss1 11/12 (6/7) i logic power supply pin. v dd should be tied to +5 v during programming. note: parentheses indicate 44-qfp otp pin number. table 21-2. comparison of s3p863a and s3c8639/c863a features characteristic s3p863a s3c8639/c863a program memory 48-kbyte eprom 32/48-kbyte mask rom operating voltage (v dd ) 3.0 v to 5.5 v 3.0 v to 5.5v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 42sdip, 44qfp 42sdip, 44qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p863a, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 21-3 below. table 21-3. operating mode selection criteria v dd v pp (test) reg/mem address (a15?a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
s3p863a otp s3c8639/c863a/p863a 21- 4 d.c. electrical characteristics table 21-4. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit input high leakage current i lih1 v in = v dd all input pins except x in , x out ? ? 3 a i lih2 v in = v dd ; x out only ? ? 20 i lih3 v in = v dd ; x in only 2.5 6 20 input low leakage current i lil1 v in = 0 v; all input pins except x in , x out , reset , hsync-i and vsync-i ? ? ? 3 i lil2 v in = 0 v; x out only ? ? ? 20 i lil3 v in = 0 v; x in only ? 2.5 ? 6 ? 20 output high leakage current i loh1 v out = v dd ? ? 3 output low leakage current i lol1 v out = 0 v ? ? ? 3 pull-up resistor r u1 v in = 0 v; v dd = 5 v 10% port 3.7?3.4 20 47 80 k w r u2 v in = 0 v; v dd = 5 v 10% reset only 150 280 480 pull-down resistor r d v in = 0 v; v dd = 5 v 10% hsync-i and vsync-i 150 300 500 supply current (note) i dd1 v dd = 5 v 10% operation mode; 12 mhz crystal c1 = c2 = 22pf ? 10 20 ma i dd2 v dd = 5 v 10% idle mode; 12 mhz crystal c1 = c2 = 22pf 4 8 i dd3 v dd = 5 v 10% stop mode 100 150 a note: supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.

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